Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

TL;DR

A developer has shared a version of the Project Oberon system running on RISC-V hardware, replacing the original RISC-5 architecture. This development demonstrates the OS’s portability and opens new possibilities for hardware compatibility.

A developer has publicly shared a version of the Project Oberon system that runs on RISC-V architecture, replacing the original support for RISC-5 processors. This achievement, announced on Show HN, marks a significant step in demonstrating Oberon’s portability across different hardware platforms and highlights ongoing efforts to modernize and adapt the OS to open hardware standards.

The developer, known as ‘Elias,’ posted on Show HN that they have successfully ported the Project Oberon operating system to run on RISC-V hardware. The original Oberon system was designed for the RISC-5 processor, which is part of the original Oberon hardware designed by Niklaus Wirth and colleagues at ETH Zurich. According to Elias, the port involves adapting the OS’s low-level code to support RISC-V’s instruction set and hardware interfaces, with functional system boot and basic operations confirmed.

While the port is still in early stages, Elias reported that the system can now run Oberon’s environment on RISC-V hardware, including basic file operations and user interface components. The effort is documented in a detailed blog post linked within the Show HN thread, where Elias describes the technical challenges faced and solutions implemented. The project aims to demonstrate that Oberon, originally tied to a specific architecture, can be re-targeted to modern open hardware platforms.

At a glance
updateWhen: announced March 2024
The developmentA Show HN post announced that a version of the Project Oberon operating system now runs on RISC-V processors, replacing the original RISC-5 support.

Implications for Hardware Compatibility and Open OS Development

This development matters because it shows that Project Oberon, a historically influential operating system and programming environment, can be ported to RISC-V hardware. RISC-V, as an open-source instruction set architecture, is gaining traction among hardware developers seeking alternatives to proprietary architectures. Porting Oberon to RISC-V could facilitate wider adoption of the OS in open hardware projects and educational settings. It also underscores the potential for legacy systems and specialized OSes to be modernized for current and future hardware platforms, promoting sustainability and innovation in OS development.

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RISC-V development board

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Historical and Technical Background of Oberon and RISC-V

Project Oberon was developed in the 1980s by Niklaus Wirth and colleagues at ETH Zurich, originally designed as both a programming language and operating system for specialized hardware based on the RISC-5 processor. The OS has been influential in academic and experimental computing but saw limited mainstream hardware support. RISC-V, an open-source instruction set architecture introduced in 2010, has become increasingly popular among hardware designers, researchers, and hobbyists due to its flexibility, modularity, and lack of licensing restrictions.

Prior to this port, Oberon was primarily associated with the RISC-5 architecture, which is now largely obsolete. The port to RISC-V represents a significant technical challenge, involving adapting low-level hardware interfaces, memory management, and device drivers to the new architecture. The effort aligns with broader trends of modernizing legacy systems and exploring open hardware solutions.

“Porting Oberon to RISC-V was challenging but rewarding; it proves the OS’s design is portable and adaptable to modern open architectures.”

— Elias, developer

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Open source RISC-V processor

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Extent of System Functionality and Future Stability

It is not yet clear how fully functional the RISC-V port of Oberon is beyond basic operations. The scope of device support, stability, and performance under load remains to be tested. Additionally, whether the port will be maintained and extended by the community is still uncertain, as the project is currently in early development stages.

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RISC-V compatible motherboard

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Next Steps for Development and Community Engagement

The developer plans to further refine the RISC-V port, adding support for additional hardware features and improving system stability. Community feedback and contributions are encouraged to expand functionality. Future milestones include achieving a fully operational Oberon environment on various RISC-V hardware platforms and documenting the porting process for broader adoption.

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Project Oberon OS hardware

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Key Questions

What is Project Oberon?

Project Oberon is an operating system and programming environment developed in the 1980s by Niklaus Wirth and colleagues at ETH Zurich, known for its simplicity and educational value.

Why is porting Oberon to RISC-V significant?

It demonstrates that Oberon can be adapted to modern open hardware architectures, potentially broadening its use in education, research, and hobbyist projects based on RISC-V.

Is the RISC-V port fully functional?

Currently, only basic operations have been confirmed. The port is in early stages, and full functionality, stability, and hardware support are still being developed.

Can this port be used in production systems?

At this stage, it is primarily a proof of concept and experimental effort. It is not recommended for production use until further development and testing are completed.

How can I contribute to this project?

The developer has shared details on a blog linked within the Show HN post. Interested contributors can review the code, provide feedback, or help extend hardware support.

Source: hn

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